datasheet triple pll field prog. spread spectrum clock synthesizer ics281 idt? / ics? triple pll field prog. spread spectrum clock synthesizer 1 ics281 rev f 051310 description the ics281 field programmable spread spectrum clock synthesizer generates up to three high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. it is designed to replace crystals, crystal oscillators and stand alone spread spectrum devices in mo st electronic systems. using idt?s versaclock tm software to configure plls and outputs, the ics281 contains a one-time programmable (otp) rom for field programmability. programming features include input/output frequencies, spread spectrum amount and eight selectable configuration registers. using phase-locked loop (pll) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. it can replace multiple crystals and oscillators, saving b oard space and cost. the ics281 is also available in factory programmed custom versions for high-volume applications. features ? packaged as 16-pin tssop ? pb-free, rohs compliant ? eight addressable registers ? replaces multiple crystals and oscillators ? output frequencies up to 200 mhz at 3.3 v ? configurable spread spectrum modulation ? input crystal frequency of 5 to 27 mhz ? input clock frequency of 3 to 166 mhz ? up to three reference outputs ? operating voltages of 3.3 v ? vddo output control from 1.8 v to 3.3 v ? controllable output drive levels ? advanced, low-power cmos process block diagram crystal oscillator gnd 3 3 vdd pdts pll2 pll3 divide logic and output enable control s2:s0 clk1 clk3 clk2 3 otp rom with pll values x2 crystal or clock input external capacitors are required with a crystal input. x1/iclk pll1 with spread spectrum vddo
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 2 ics281 rev f 051310 pin assignment pin descriptions 12 1 11 2 10 3 9 4 s0 5 s1 6 vdd 7 gnd 8 vdd pdts s2 gnd gnd vdd vddo clk1 clk3 16 15 14 13 clk2 x2 16 pin (173 mil) tssop x1/iclk pin number pin name pin type pin description 1 gnd power connect to ground. 2 s0 input select pin 0. internal pull-up resistor. 3 s1 input select pin 1. internal pull-up resistor. 4vddpower connect to +3.3 v. 5 vddo power power supply for outputs. 6 clk1 output output clock 1. weak internal pull-down when tri-state. 7 gnd power connect to ground. 8 x1 xi crystal input. connect this pin to a crystal or external input clock. 9 x2 xo crystal output. connect this pin to a crystal. float for clock input. 10 vdd power connect to +3.3 v. 11 clk2 output output clock 2. weak internal pull-down when tri-state. 12 clk3 output output clock 3. weak internal pull-down when tri-state. 13 gnd power connect to ground. 14 pdts input power-down tri-state. powers down entire chip and tri-states clock outputs when low. internal pull-up resistor. 15 vdd power connect to +3.3 v. 16 s2 input select pin 2. internal pull-up resistor.
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 3 ics281 rev f 051310 external components the ics281 requires a minimum number of external components for proper operation. series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitors as with any high-performance mixed-signal ic, the ics281 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias on the decoupling circuit. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 20 pf [(16-6) x 2 = 20]. ics281 configuration capabilities the architecture of the ics281 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. the frequency multiplier pll provides a high degree of precision. the m/n values (t he multiplier/divide values available to generate the target vco frequency) can be set within the range of m = 1 to 1024 and n = 1 to 32,895. the ics281 also provides separate output divide values, from 2 through 63, to allow the two output clock banks to support widely differing frequency values from the same pll. each output frequency can be represented as: output drive control the ics281 has two output drive settings. for vddo=vdd, low drive should be selected when outputs are less than 100 mhz. high drive should be selected when outputs are greater than 100 mhz. for vddo<2.8 v, high drive should be selected for all output frequencies. (consult the ac electrical characteristics for output rise and fall times for each drive option.) idt versaclock software idt applies years of pll optimization experience into a user friendly software that accepts the user?s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. the user does not need to have prior pll experience or determine the optimal vco frequency to support multiple output frequencies. versaclock software quickly evaluates accessible vco frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. the user may evaluate output accuracy, performance trade-off scenarios in seconds. spread spectrum modulation the ics281 utilizes frequency modu lation (fm) to distribute energy over a range of frequencies. by modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system?s electromagnetic interference (emi). the modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. outputfreq reffreq m n ---- - ? =
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 4 ics281 rev f 051310 spread spectrum modulation can be applied as either ?center spread? or ?down spread?. during center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. the effective average frequency is equal to the target frequency. in applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. in this case, the maximum frequency, including modulation, is the target frequency. the effective average frequency is less than the target frequency. the ics281 operates in both center spread and down spread modes. for center spread, the frequency can be modulated between 0.125% to 2.0%. for down spread, the frequency can be modulated between -0.25% to -4.0%. both output freq uency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common vco frequency can be identified. spread spectrum modulation rate the spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. for applications requiring the driving of ?down-circuit? plls, zero delay buffers, or those adhering to pci standards, the spread spectrum modulation rate should be set to 30-33 khz. for other applications, a 120 khz modulation option is available. absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the ics281. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions parameter condition min. typ. max. units supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+0.5 v clock outputs referenced to gnd -0.5 vdd+0.5 v storage temperature -65 150 c soldering temperature max 10 seconds 260 c junction temperature 125 c parameter min. typ. max. units ambient operating temperature (ics281pg/pglf) 0 +70 c ambient operating temperature (ics281pgi/pgilf) -40 +85 c power supply voltage (measured in respect to gnd) +3.135 +3.3 +3.465 v power supply ramp time 4 ms
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 5 ics281 rev f 051310 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c note 1: example with 25 mhz crystal input, three unloaded 33.3 mhz outputs and vdd = vddo = 3.3 v. parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.465 v vddo voltage 1.80 vdd v operating supply current input high voltage idd config. dependent - see versaclock tm estimates ma three 33.3333 mhz outs, vdd=vddo=3.3v; pdts = 1, no load, note 1 20 ma pdts = 0, no load, note 1 500 a input high voltage v ih s2:s0 vdd/2+1 v input low voltage v il s2:s0 0.4 v input high voltage, pdts v ih vdd-0.5 v input low voltage, pdts v il 0.4 v input high voltage v ih iclk vdd/2+1 v input low voltage v il iclk vdd/2-1 v output high voltage (cmos high) v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -8 ma (low drive); i oh = -12 ma (high drive) 2.4 vddo-0.4 v output low voltage v ol i ol = 8 ma (low drive); i ol = 12 ma (high drive) 0.4 v short circuit current i os low drive 40 ma high drive 70 nom. output impedance z o 20 ? internal pull-up resistor r pus s2:s0, pdts 190 k ? internal pull-down resistor r pd clk outputs 120 k ? input capacitance c in inputs 4 pf
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 6 ics281 rev f 051310 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c note 1: measured with 15 pf load. note 2: duty cycle is configuration dependent. most configurations are min 45% / max 55%. thermal characteristics parameter symbol conditions min. typ. max. units input frequency f in fundamental crystal 5 27 mhz clock input 3 166 mhz output frequency vddo=vdd 0.314 200 mhz 1.8 v< vddo< 2.8 v 0.314 150 mhz output rise/fall time t of 80% to 20%, high drive, note 1 1.0 ns output rise/fall time t of 80% to 20%, low drive, note 1 2.0 ns output rise/fall time t of 80% to 20%, high drive, 1.8 v< vddo< 2.8 note 2 2.0 ns duty cycle note 2 40 49-51 60 % output frequency synthesis error configuration dependent tbd ppm power-up time pll lock-time from power-up 410ms pdts goes high until stable clk output, spread spectrum off 0.6 2 ms pdts goes high until stable clk output, spread spectrum on 47ms one sigma clock period jitter configuration dependent 50 ps maximum absolute jitter t ja deviation from mean. configuration dependent + 200 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 7 ics281 rev f 051310 marking diagrams notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?i? denotes industrial temperature range (if applicable). 4. ?l? denotes pb (lead) free package. 5. bottom marking: country of origin. 1 8 9 16 281pgl ###### yyww 1 8 9 16 281pgil ###### yyww
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 8 ics281 rev f 051310 package outline and package dimensions (16-pin tssop, 173 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 24 d e1 e seating plane a1 a a2 e - c - b .10 (.004) c c l millimeters inches symbol min max min max a ? 1.20 ? .047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.450.75.018.030 0 8 0 8 16
ics281 triple pll field prog. spread spectrum clock synthesizer eprom clock synthesizer idt? / ics? triple pll field prog. spread spectrum clock synthesizer 9 ics281 rev f 051310 ordering information ?lf? suffix to the part numb er deontes the pb-free conf iguration, rohs compliant. the281g-xxlf and 281 gi-xxlf are factory programmed versions of the 281pglf and 281pgilf. a unique ?-xx? suffix is assigned by the factory for each custom conf iguration, and a separate da ta sheet is kept on file. fo r more information on custo m part numbers programmed at the factory, please cont act your local idt sales and marketing representative. while the information presented herein has been checked for both accuracy and reliability, idt assumes no responsibility for ei ther its use or for the infringement of any patents or other rights of third pa rties, which would result from its use. no other circuits, pa tents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary envi ronmental requirements are not re commended without additional p rocessing by idt. idt reserves the right to change any circuitry or spec ifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. versaclock tm is a trademark of idt, inc. all rights reserved. part / order number marking shipping packaging package temperature 281pglf see page 7 tubes 16-pin tssop 0 to +70 c 281pgilf tubes 16-pin tssop -40 to +85 c 281g-xxlf tubes 16-pin tssop 0 to +70 c 281gi-xxlf tubes 16-pin tssop -40 to +85 c 281G-XXLFT tape and reel 16-pin tssop 0 to +70 c 281gi-xxlft tape and reel 16-pin tssop -40 to +85 c
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